spice device model sqj463ep www.vishay.com vishay siliconix s12-2558-rev. b, 29-oct-12 1 document number: 66760 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 p-channel 40 v (d-s) mosfet description the attached spice model describes the typical electrical characteristics of the p-channel vertical dmos. the subcircuit model is extracted an d optimized over the - 55 c to + 125 c temperature ranges under the pulsed 0 v to 10 v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c gd model. all model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ?level 3 mos ? apply for both linear and switching application ? accurate over the - 55 c to + 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics ? subcircuit model schematic note ? this document is intended as a spice modeling guideline and does not constitute a commercial product datasheet. designers shou ld refer to the appropriate datasheet of the same number for guaranteed specification limits. d s dbd c gs m 1 g 3 r 1 m 2 g x r g c g d g y etcv + C
spice device model sqj463ep www.vishay.com vishay siliconix s12-2558-rev. b, 29-oct-12 2 document number: 66760 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design , not subject to production testing. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions simulated data measured data unit static gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a 1.4 - v drain-source on-state resistance a r ds(on) v gs = - 10 v, i d = - 18 a 0.008 0.007 ? v gs = - 4.5 v, i d = - 15 a 0.013 0.011 forward transconductance a g fs v ds = - 15 v, i d = - 18 a 42 45 s diode forward voltage v sd i s = - 4.5 a - 0.70 - 0.80 v dynamic b input capacitance c iss v ds = - 20 v, v gs = 0 v, f = 1 mhz 4760 4700 pf output capacitance c oss 700 625 reverse transfer capacitance c rss 400 460 total gate charge q g v ds = - 20 v, v gs = - 10 v, i d = - 18.6 a 95 97 nc gate-source charge q gs 14 14 gate-drain charge q gd 23 23
spice device model sqj463ep www.vishay.com vishay siliconix s12-2558-rev. b, 29-oct-12 3 document number: 66760 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 comparison of model with measured data (t j = 25 c, unless otherwise noted) note ? dots and squares represent measured data. i d - drain current (a) v d s - drain-to- s ource voltage (v) i d - drain current (a) c - capacitance (pf) v d s - drain-to- s ource voltage (v) q g - total g ate charge (nc) v gs - g ate-to- s ource voltage (v) i s - s ource current (a) v s d - s ource-to-drain voltage (v) r d s (on) - on-re s i s tance ( ) i d - drain current (a) v gs - g ate-to- s ource voltage (v) 0 10 20 30 40 50 60 0 2 4 6 8 10 v gs = 4 v v gs = 3 v v gs = 10 v, 7 v, 6 v, 5 v 0 10 20 30 40 50 0 1 2 3 4 5 t j = 125 c t j = - 55 c t j = 25 c 0.00 0.01 0.02 0.03 0.04 0.05 0 102030405060 v gs = 10 v v gs = 4.5 v 0 1000 2000 3000 4000 5000 6000 7000 0 10203040 c i ss c o ss c r ss 0 2 4 6 8 10 0 102030405060708090100 v d s = 20 v i d = 18.6 a 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1.0 1.2 t j = 150 c t j = 25 c
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